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International Journal of Innovation and Scientific Research
ISSN: 2351-8014
 
 
Saturday 26 May 2018

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Analysis of shift register using GDI AND gate and SSASPL using Multi Threshold CMOS technique in 22nm technology


Volume 22, Issue 2, April 2016, Pages 415–424

 Analysis of shift register using GDI AND gate and SSASPL using Multi Threshold CMOS technique in 22nm technology

N. Sathya, M. Anto Bennet, G. Hemapriya, S. Mohanambal, and A. Nandhini

Original language: English

Received 31 March 2016

Copyright © 2016 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract


Shift register in this paper possess low efficient SSASPL (Static differential Sense Amp Shared Pulsed Latch). Timing problem between pulsed latches is solved using multiple non-overlap delayed strobe signal. Here latches are grouped into several sub-shift registers. To provide better results, leakage current and leakage power are reduced with MTCMOS (Multi Threshold Complementary Metal Oxide Semiconductor) and power-delay products are further reduced using Mod-GDI(Modified Gate Diffusion Input) technique. A 16-bit shift register in 22nm technology with supply voltage VDD =200mv and consumes 0.147mW. Power consumption in percentage is 43.04% in other words power reduced in comparison to the existing systems is 14.85%. Simulation is done using Tanner EDA TOOL in 22nm technology.

Author Keywords: power-delay products, SSASPL, MTCMOS, strobe signal, Mod-GDI.


How to Cite this Article


N. Sathya, M. Anto Bennet, G. Hemapriya, S. Mohanambal, and A. Nandhini, “Analysis of shift register using GDI AND gate and SSASPL using Multi Threshold CMOS technique in 22nm technology,” International Journal of Innovation and Scientific Research, vol. 22, no. 2, pp. 415–424, April 2016.